As semiconductor devices become highly integrated, controlling performance of the semiconductor device becomes very difficult. For example, in the case of a MOS transistor, since sizes of a gate electrode, a source electrode, a drain electrode and the like are reduced, a channel length is also reduced. If the channel length is reduced as described above, SCE (short channel effect) and RSCE (reverse short channel effect) may occur. Thus, threshold voltage of the transistor may not be easily adjusted.
Further, since the driving voltage of a highly integrated semiconductor device is relatively high as compared with the size of the highly integrated semiconductor device, electrons emitted from a source may be excessively accelerated due to potential gradient of a drain. Thus, hot carriers may be generated around the drain. In this regard, an LDD (lightly doped drain) structure has been introduced in order to improve the performance of the semiconductor device having the structural weakness as described above.
According to the LDD structure, an n-LDD region positioned between a channel and source/drain attenuates drain-gate voltage around a drain junction and reduces excessive potential gradient, so that the hot carriers can be prevented from being generated. In order to obtain such an LDD structure, a technology of forming spacers at both sidewalls of a gate electrode has been introduced.
However, in the ion implantation process for forming the LDD region, defects may occur on a substrate and a semiconductor layer. Further, an ion implantation apparatus is generally expensive, has a complicated configuration, and may be difficult to operate. In addition, a manager of the apparatus may be exposed to poison gas and high voltage.
Further, in the case of integrating various devices such as PMOS transistors and NMOS transistors on the same wafer, formation of an n-type LDD pattern, n-type ion implantation, cleaning, formation of a p-type LDD pattern, p-type ion implantation, and cleaning must be repeatedly performed.
Furthermore, when the n-type LDD region is formed and a cleaning process is performed, an oxide layer of a polysilicon layer may be partially damaged. Thus, an oxidation process must be performed before p-type ions are implanted.
In addition, sidewalls are formed at the sides of the gate electrode in order to attenuate stress and enhance adhesion between the spacers and the electrode. Then, the spacers are formed through deposition, etch and cleaning processes.
As described above, the LDD technology requires a complicated procedure, so that process efficiency is degraded and the manufacturing time and cost may be increased.